1. Field of the Invention
This invention relates to a planarization process for integrated circuit structures. More particularly, this invention relates to a planarization process which utilizes an initial ECR plasma deposition to achieve a high density vertical deposition of a conformal insulation layer with a high aspect ratio; a low melting inorganic planarization material to planarize the ECR plasma deposited layer; and an optional CVD layer applied over the planarized ECR plasma layer.
2. Description of the Related Art
In the formation of integrated circuit structures, patterning of layers, to permit formation, on a substrate, of active devices such as transistors, passive devices such as resistors, and metal lines to interconnect devices, can result in the formation of uneven surfaces.
Conventionally, a layer of insulating material such as silicon oxide is applied over such uneven surfaces, to permit the formation of further patterned layers thereover. However, the silicon oxide tends to conform to the underlying topography resulting in the creation of a nonplanar or stepped surface. It is very difficult to pattern further layers over such an uneven surface using standard lithography techniques.
It has, therefore, become the customary practice to apply planarizing layers of either photoresist or organic-based glass materials, such as "SOG" (Spin On Glass) which will etch at about the same rate as the underlying silicon oxide insulating layer. The structure is then anisotropically etched to remove the planarizing layer, as well as raised portions of the underlying silicon oxide layer.
However, both photoresist and SOG have what is called a loading effect. This means that the etch rate of these materials depends upon how much of the insulating layer, e.g., the silicon oxide layer, is exposed. Thus, achieving an equal etch rate of both insulating material (silicon oxide) and the sacrificial or planarizing material is very difficult and the etch rate is, therefore, dependent upon the geometry of the structure. Furthermore, when the spaces between raised portions are less than about 1.5 microns, the spinning process of applying either of these two planarizing materials is not effective.
The above described planarizing materials also have limited step coverage and are limited with respect to the total amount or thickness of these materials which can be deposited. Furthermore, since these planarizing materials are dispersed in organic binders and solvents, prior to application of such planarizing materials, the integrated circuit structure must be removed from a vacuum chamber in which the insulating layer such as silicon oxide is deposited, e.g., by CVD methods, in order to coat the structure with the planarizing layer. After such coating, the solvent in the planarizing coating must be allowed to evaporate and the planarizing coating must then be baked to remove further solvents and to harden the coating prior to the etching step, which is conventionally a dry etching process which is also usually carried out in a vacuum chamber.
These problems were addressed in parent U.S. Pat. application, Marks et al Ser. No. 269,508, filed Nov. 10, 1988, entitled METHOD FOR PLANARIZING AN INTEGRATED CIRCUIT STRUCTURE USING LOW MELTING INORGANIC MATERIAL, cross-reference to which is hereby made. In that application, there is described and claimed a method for planarizing such structures using a planarizing layer of a low melting inorganic glass which is deposited over a conformal insulating layer such as a silicon oxide formal insulating layer such as a silicon oxide layer.
However, the initial conformal insulating layer, e.g. a layer of silicon oxide, which is conventionally applied over the underlying metal lines or other patterned layers using CVD deposition techniques, does not always adequately fill in those regions between closely spaced apart metal lines or other raised parts of the underlying integrated circuit structure. This can result in the formation of voids in those portions of the silicon oxide layer deposited between such closely spaced apart raised parts of the integrated circuit structure.
A form of deposition known as electron cyclotron resonance (ECR) plasma deposition, is described in Matsuo et al U.S. Pat. No. 4,401,054; Matsuo et al U.S. Pat. No. 4,492,620; and Ghanbari U.S. Pat. No. 4,778,561 (cross-reference to which three patents is hereby made); as well as in an article by Machida et al, entitled "SiO.sub.2 Planarization Technology With Biasing and Electron Cyclotron Resonance Plasma Deposition for Submicron Interconnections", published in J. Vac. Sci. Technology B, Vol. 4, No. 4, Jul/Aug 1986, at pp. 818-821.
The ECR plasma deposition process described in these publications provides deposition of material via a plasma wherein a plasma formation chamber is surrounded by one or more magnetic coils to generate a magnetic field which produces an electron cyclotron resonance in the plasma formation chamber with the axis of the magnetic field extending toward a deposition chamber in a divergent manner. The resulting deposition, for example, of SiO.sub.2 from oxygen and silane gases, is a more dense conformal insulating layer with a high aspect ratio to provide better filling of the regions between closely spaced apart lines, thus eliminating or at least mitigating the problem of void formation in the insulation material deposited in such areas.
However, while such an ECR plasma deposited conformal insulating layer does solve the void formation problem discussed above, the ECR plasma process is considerably slower than a conventional CVD deposit. Furthermore, the planarization problems associated with silicon oxide layers, as discussed in the aforementioned Marks et al parent patent application, also apply to the formation of a silicon oxide layer using ECR plasma deposition techniques as well.
It would, therefore, be desirable to provide a planarization process wherein the problem of void formation could be eliminated while expediting the planarization process and without the need for removing the integrated circuit structure from the vacuum apparatus used to deposit one or more of the planarization layers.